1. Field of the Invention
The present invention relates to computer memory management and, more specifically, to a computer architecture that stores data units based on known memory location latencies.
2. Description of the Prior Art
Virtually all computer circuits employ some sort of digital memory to store data. Such memory can include a combination of different types of memory devices, including one or more of the following: on-chip memory (such as array of registers), on board memory (such as cache memory), main memory (such as DRAM memory chips on a different circuit board from a processor), flash memory (such as memory device that can be plugged into a special reader or a USB port), and disk memory (such as a hard drive).
Some data units (which can include any method of grouping data) residing in a memory space are less-used than other data units stored on the same memory space. However, different parts of a computer's memory space exhibit different memory latencies (the amount of time it takes for data to be transferred from a memory location to the entity that requested it). For example, memory chips closest to a memory buffer are likely to have a lower latency than memory chips farther away from the memory buffer.
Most memory devices can be classified in terms of relative speed. For example, on-chip memory is usually faster that on-board memory, and both are usually much faster than disk memory. However, sometimes certain portions of a relatively slower memory device may actually have a lower latency than portions of a relatively faster memory device. Therefore, placing frequently used data units in a slower portion of the faster memory device instead of the faster portion of the slower memory device would result in an inefficient usage of memory space.
In many memory applications, dynamic random access memory (DRAM) chips are placed at similar rank positions in an array, thereby creating a flat memory structure in which all of the memory is accessible for data writes and reads equally from the memory controller. However, in current industry-standard schemes, such as fully buffered dual in-line memory module (FBDIMM), there is a non-uniform access time to each layer of memory through buffers on the memory chips. Memory controllers supporting the current FBDIMM standard can take advantage of lower latencies for closer DIMM chips, but do not deliberately map heavily utilized data closer to the memory controller, or less heavily utilized data farther away from the controller.
Current memory devices include caches (for processors), which typically place data into sorted levels (L1/L2/L3), but that require space for a copy (or placeholder) of the original data be maintained either in main memory or in a direct access storage device (DASD) such as a hard drive. This is an inefficient use of memory, both in terms of added memory usage and added overhead to keep placeholders of data and to ensure that the data are current.
The latency of physical memory locations can change over time. This can be due to various factors. For example, environmental conditions can cause changes in memory latency. Also, usage patterns can change memory latency. For example, when several contiguous memory locations are used computationally in a tight loop, other nearby memory locations might experience an increase in latency due to local traffic on the memory bus servicing the memory locations.
Therefore, there is a need for memory management system that measures memory latency dynamically and that determines the location of where a data unit is stored based on the relative frequency of use of the data unit and the latency of the storage location.
There is also a need for a memory management system that stores data units dynamically in a hierarchical memory space, segregated according to a current value of latency.